A well-known standard for use in testing integrated circuits and other types of digital systems has been developed by the Joint Test Action Group (JTAG) and is defined in Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, “IEEE Standard Test Access Port and Boundary Scan Architecture,” IEEE, New York, N.Y., October, 1993, which is incorporated by reference herein. For example, in the context of an integrated circuit, the IEEE 1149.1 standard defines test logic that can be included in an integrated circuit to provide standardized approaches to testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate, testing the integrated circuit itself, and observing or modifying circuit activity during normal circuit operation. The test logic includes a boundary-scan register as well as other elements and is accessible through a Test Access Port (TAP) associated with the integrated circuit. The test logic allows test instructions and associated test data to be fed into the integrated circuit, and allows the results of execution of the instructions to be subsequently read out. All information, i.e., test instructions, test data and test results, are communicated in a serial format. The integrated circuit test process is also commonly referred to as “debugging.”
Many recently-developed integrated circuits include multiple processors configured to implement a variety of so-called “system on a chip” solutions. The processor cores may be homogeneous, i.e., have the same processor architecture, or heterogeneous, i.e., have different processor architectures. The higher levels of integration associated with such multiple processor devices generally require additional package input/output (I/O) capacity, i.e., additional package pins and associated internal bonding pads, wiring etc. However, this requirement is in conflict with other requirements, such as portable operation, that generally require lower power and thus a lower package I/O capacity. As a result, it is important that the integrated circuit test functions utilize as few pins as possible.
The above-described IEEE 1149.1 standard has been used successfully to minimize I/O capacity requirements for debug access to integrated circuits with a single processor core or multiple homogeneous processor cores on the same scan chain.
For example, a conventional approach to debugging of an integrated circuit with multiple homogeneous processors is described in L. Goudge, “Debugging Embedded Systems,” ARM White Paper, www.arm.com, 1998. In this approach, if a user wishes to examine the state of more than one processor during a debugging session, then this may be achieved synchronously by setting up “debug halt” conditions independently within each processor while the system is running. Through use of the TAP controller state machine, all of the processors may then be stopped simultaneously. Similarly, at the end of the debugging session, “debug restart” conditions may be set up in each processor and again through use of the state machine, the processors may be restarted simultaneously. This approach requires that all of the processors be homogeneous, and all of the processors must be involved in the condition setting in order to provide the synchronous stopping and restarting.
Another conventional approach for IEEE 1149.1 testing of an integrated circuit with homogeneous processors is the ScanProgrammer from ASSET InterTech, www.asset-intertech.com. This approach uses a single database that is loaded with Serial Vector Format (SVF) data to assemble scans for an IEEE 1149.1 scan chain.
Yet another known approach is the Global Embedded Processor Debug Interface Standard (GEPDIS), www.ieee-isto.org/Nexus5001, which describes the Nexus 5001 Forum™ Standard for a global embedded processor debug interface. This is an open industry standard that provides a general-purpose interface for the software development and debug of embedded processors.
A number of significant problems arise in the application of the IEEE 1149.1 standard to integrated circuits and other types of digital systems which include multiple heterogeneous processors. For example, conventional application of the IEEE 1149.1 standard to multiple heterogeneous processors often requires that a TAP controller for one or more of the processors be redesigned to support asynchronous control. This may require modifications of components not designed to be easily modified or tested. Other conventional approaches may require special hardware to mediate access to multiple TAP controllers in a manner that often violates the IEEE 1149.1 standard and does not easily allow for synchronous control of the multiple processors.
A possible software approach to the problems associated with testing multiple heterogeneous processors is to build a debugger that treats the target system as a single device and merges stand-alone debug systems for all of the devices to be controlled. Unfortunately, the drawbacks of this approach are numerous. For example, the source code for each debug system must be modified, and this source code can be difficult to access. In addition, the resulting debugger supports only one or at most a handful of combinations of devices. Furthermore, upgrades to the stand-alone debug systems must be laboriously reintegrated into the merged debugger.
In view of the foregoing, it is apparent that a need exists for an improved control mechanism for use in testing of integrated circuits and other types of digital systems which incorporate multiple and possibly heterogenous processors.